1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that stores a defective address by a nonvolatile memory element.
2. Description of Related Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), the number of memory cells that do not function properly (hereinafter, “defective cells”) increases with an increase of a memory density. To solve this problem, auxiliary memory cells called “redundant cells” are prepared in advance in the semiconductor memory device. By replacing a defective cell with a redundant cell, a memory address of the defective cell (hereinafter, “defective address”) is saved. A detection of the defective cell and a replacement with the redundant cell are performed in a wafer state at a time of manufacturing the semiconductor memory device. Specifically, the defective address is detected at an operation test that is performed in the wafer state, and the detected defective address is stored in an address storing circuit included in the semiconductor memory device. With this mechanism, when the defective address is designated as an access destination, the redundant cell becomes an actual access destination instead of the defective cell, by which the defective address is saved.
In many cases, a fuse element is used as a memory element for storing the defective address. The fuse element is electrically in a conductive state in the initial state and is changed to a nonconductive state (an insulation state) with line-breaking by an irradiation with a laser beam. Information of one bit can be represented by the conductive state and the nonconductive state of one fuse element. Therefore, by irradiating a plurality of fuse elements with the laser beam in a selective manner, a desired defective address can be stored in a nonvolatile manner. The process of storing the defective address in the fuse elements is called “programming”.
However, the fuse element has a problem that a passivation layer is collaterally damaged at a time of an irradiation with the laser beam. Because of this problem, in recent years, a nonvolatile memory element called an antifuse element is used to save the defective address. The antifuse element is in a nonconductive state in an initial state and is changed to a conductive state with an insulation-breakdown by an application of a high voltage. The change of resistance in the antifuse element before and after programming is opposite to that in the fuse element. Because the passivation layer is not damaged at a time of the programming, the reliability of a product can be enhanced.
However, the antifuse element has a problem of its memory stability because the state of the antifuse element can be returned from the conductive state to the nonconductive state with time. To deal with this problem, a method of enhancing the memory stability has been proposed, in which two or more antifuse elements are assigned per bit, and if at least one antifuse element is in an insulation-breakdown state, it is determined that the bit is in a programmed state (see, for example, Japanese Patent Application Laid-open No. 2007-80302).
FIG. 10 is a circuit diagram showing an example of a conventional antifuse memory circuit in which two antifuse elements are assigned per bit. An antifuse memory circuit 150 shown in FIG. 10 is a circuit for storing 1-bit data. The antifuse memory circuit 150 includes two sets of an antifuse element AF, a driver transistor DR, a load transistor LD, and a decoder circuit 100. In the following explanations, when collectively referring to antifuse elements AF(A) and AF(B) or making no distinction between them, it is simply called “antifuse element AF”. The same goes for other elements.
The anti fuse element AF is a PMOS (Positive channel Metal Oxide Semiconductor) transistor in which a source and a drain are short circuited, and a gate insulation is in any one of a non-breakdown state (hereinafter, “first logical state”) or a breakdown state (hereinafter, “second logical state”). The initial state is the first logical state.
Source-drain connection nodes of the antifuse elements AF(A) and AF(B) are commonly connected to a predetermined voltage line VBBSVT. A potential of the voltage line VBBSVT is called “reference potential”. Gates of the antifuse elements AF(A) and AF(B) are commonly connected to a predetermined voltage line VPPSVT via driver transistors DR(A) and DR(B), respectively. A potential of the voltage line VPPSVT is called “program potential”.
Decoder circuits 100A and 100B are connected to gates of the driver transistors DR(A) and DR(B), respectively. When a write signal AFWRT is asserted in a state where a row address signal XA indicates a predetermined value, the decoder circuits 100A and 100B switch on the driver transistors DR(A) and DR(B), respectively. When the driver transistors DR(A) and DR(B) are switched on, the program voltage VPPSVT is applied to the antifuse elements AF(A) and AF(B), so that an insulation-breakdown of gate insulation layers occurs. As a result, the states of the antifuse elements AF(A) and AF(B) are changed from the first logical state to the second logical state. Of course, the program voltage VPPSVT needs to be high enough to achieve the insulation-breakdown of the antifuse element AF.
When a load signal LOAD is asserted, both load transistors LD(A) and LD(B) are switched on. At this time, a determining circuit 120 detects gate potentials of the antifuse elements AF(A) and AF(B). A detected potential is different according to the states of the antifuse elements AF(A) and AF(B), whether both of them are in the first logical state or at least one of them is in the second logical state. In this manner, the antifuse memory circuit 150 represents 1-bit data by taking a wired OR of the two antifuse elements AF(A) and AF(B).
Normally, the logical states of the antifuse elements AF(A) and AF(B) coincide with each other. However, even when both the driver transistors DR(A) and DR(B) are switched on, there can be a case where only one of the antifuse elements AF(A) and AF(B) succeeds in the insulation-breakdown. In this case, a re-application of the program voltage can solve the problem. For example, assume that the insulation-breakdown of the antifuse element AF(B) fails while the insulation-breakdown of the antifuse element AF(A) is successful. In this case, when the decoder circuit 100B switches on the driver transistor DR(B) with the decoder circuit 100A switching off the driver transistor DR(A), it becomes possible to apply the program voltage only to the driver transistor DR(B) for which the insulation-breakdown failed. Because the two driver transistors DR(A) and DR(B) can be individually controlled by the two decoder circuits 100A and 100B, it is easy to achieve the insulation-breakdown for both the antifuse elements AF(A) and AF(B) without fail.
FIG. 11 is a circuit diagram showing another example of a conventional antifuse memory circuit in which two antifuse elements are assigned per bit. In an antifuse memory circuit 152 shown in FIG. 11, not only the decoder circuit 100 is provided for each antifuse element AF, but also the determining circuit 120 is provided for each antifuse element. Outputs of determining circuit 120A and 120B are subject to a logical sum by an OR gate 122.
In the case of the antifuse memory circuit 152, an output of the OR gate 122 is changed according to the states of the antifuse elements AF(A) and AF(B), whether both of them are in the first logical state or at least one of them is in the second logical state. The basic operation principle is the same as that of the antifuse memory circuit 150 shown in FIG. 10.
However, because the decoder circuit 100 is assigned for each antifuse element AF in the antifuse memory circuits 150 and 152, there is a problem that an occupation dimension of the decoder circuit 100 is large. Such a problem can occur not only in a semiconductor memory device employing the antifuse element AF, but also in general semiconductor devices including a nonvolatile memory element in which information is stored by an application of the program voltage.